The present invention relates to a delay circuit in a data processing system, and more particularly, to a digitally adjustable resistor applied to the construction of a variable-delay element.
Data processing systems, such as microprocessors, may include a circuit designed to distribute a reference signal called a clock to synchronize the processing of data. The clock may be distributed to multiple elements acting as receivers in the data processing systems. The closer the sequential elements are to receiving the clock at the same time, the faster the data processing systems can be. Delay elements may compensate the undesired delay variations experienced by the clock when the clock travels toward the receivers, thereby increasing the system speed.